Digital computer systems have a history of continually increasing the speed of the processors used in the system. As computer systems have migrated towards multiprocessor systems, sharing information between processors and memory systems has also generated a requirement for increased speed for the off-chip communication networks. Designers usually have more control over on-chip communication paths than for off-chip communication paths. Off-chip communication paths are longer, have higher noise, impedance mismatches, and have more discontinuities than on-chip communication paths. Since off-chip communication paths are of lower impedance, they require more current and thus more power to drive.
When using inter-chip high-speed signaling, noise and coupling between signal lines (crosstalk) affects signal quality. One way to alleviate the detrimental effects of noise and coupling is through the use of differential signaling. Differential signaling comprises sending a signal and its complement to a differential receiver. In this manner, noise and coupling affect both the signal and the complement equally. The differential receiver only senses the difference between the signal and its complement as the noise and coupling represent common mode signals. Therefore, differential signaling is resistant to the effects that noise and crosstalk have on signal quality.
When high speed data is transmitted between chips, the signal lines are characterized by their transmission line parameters. High speed signals are subject to reflections if the transmission lines are not terminated in an impedance that matches the transmission line characteristic impedance. Reflections may propagate back and forth between driver and receiver and reduce the margins when detecting signals at the receiver. Some form of termination is therefore usually required for all high-speed signals to control overshoot, undershoot, and increase signal quality. For differential signaling, parallel transmission lines are used. Each transmission line may be terminated with respect to their individual characteristic impedance or the differential pair may be terminated with a resistance between the two transmission lines equal to the differential line impedance.
Transmission line systems are characterized by noise, propagation speed, losses, and reflections due to imperfect terminations. Therefore, received signals do not transition between logic levels in a repeatable fashion. Even when triggered to transition to a logic level at the same clock time, line drivers may not do so exactly the same every time. These variations in timing and voltage levels may be viewed by using an oscilloscope system to view a received signal in a time window. A snapshot of the signal during this time window may be displayed by triggering the oscilloscope system to start the time sweep at a clock time synchronous with the clock that generated the data signal. The resulting logic state transitions of the data signal will appear as an “eye diagram” wherein the rise and fall times and the logic one and logic zero voltage levels will be “smeared” to an extent depending on their variability with respect to the triggering clock transitions and any variability in the measuring system.
There is no “one” eye diagram for a data transmission system as the resulting display will depend on how the clock trigger signal at the receiver was derived. Some examples of possible trigger signals are the following:                1) a clock signal trigger at the same rate and synchronous with the data signal.        2) a divided clock trigger signals at some divide ratio of the data rate often related to a power of 2, e.g., 4, 16, etc.        3) a pattern trigger which is a signal that provides a trigger once per pattern repetition.        4) the data itself may be used as a trigger.        5) lastly, the trigger signal is derived by using clock recovery on the data signal.        
Each of these methods provide different results when used to construct the eye pattern. The clock trigger in 1) provides a classical eye diagram containing all possible bit transitions in one display. The divided clock trigger in 2) also produces an eye diagram, and this may be useful when the instrument being used to generated the eye diagram has a trigger input bandwidth lower than the data rate of the signal being viewed. This method will produce a good eye diagram unless the pattern length of the data signal divided by the divide ratio is an integer. In this cases the trigger signal will coincide with the same bits in the pattern each time while consistently missing other parts of the pattern. This will lead to an incomplete eye diagram.
The pattern trigger in 3) is used to display individual bits in the data pattern. If the pattern is long and the view time encompasses only a few bit transitions, then a particular group of bits will be viewed each triggered sweep. To view the entire pattern, requires that the view time trigger be delayed from the pattern trigger. This is done using the scope time base and may lead to increased apparent jitter on the displayed signal due to weaknesses in the time base circuitry.
Triggering on the data in 4) is the least desirable method of constructing the eye diagram and should only be used as a quick look-see. Long runs of identical characters provide no transitions to trigger from and so a complete eye diagram is almost impossible to achieve.
Triggering on a recovered clock in 5) while entailing increased complexity does have some advantages as listed:                Works well when the actual clock signal is not available        In cases when the distance between transmitter and receiver is very long, the relationship between the received data and transmit clock may be corrupted        Some standards require analysis of the eye diagram as “seen” by the receiver, especially for jitter testing        
Circuits that are used for clock recovery typically have a loop bandwidth that removes jitter from the recovered clock signal that is present on the data signal. Depending on the measurements to be made this affect may be good or bad and needs to be understood.
Narrow loop bandwidth in clock recovery gives a stable clock as the reference and any jitter in the data eye diagram will be displayed. This is a useful absolute measure but might not properly represent the jitter “seen” by a real system if the receiver also uses clock recovery to track the data to remove jitter.
Wide loop bandwidth lets through more of the jitter in the recovered clock signal. This results in the recovered clock tracking the jitter in the data signal so that the resulting eye diagram may have very little jitter present. Conversely, if there is delay between the data signal and the trigger signal, then the delayed recovered clock trigger may be moving in opposite direction from the data signal resulting in the eye diagram showing twice as much jitter as was present on the data signal.
While these various ways of generating a trigger signal result in variable eye diagrams, most measurement standards specify what type of trigger scheme is required to make particular measurements.
While eye diagrams provide accessible and intuitive view of parametric performance, data systems are ultimately judged on their ability to transmit data with low error rates. Error testing will provide an overall measure of how well a system is performing but does little to help in understanding the underlying causes for lower that expected performance.
A perfect eye diagram would show all parametric aspects of all possible bit sequences no matter how infrequent some effects may occur. This would result in a “high information depth.” However, eye diagrams are typically composed of voltage/time samples of the original data that are acquired at some sample rate that may be orders of magnitude slower that the actual data rate. For sampling oscilloscopes, this may be 105 samples per second for a 10 Gb/s (digital pattern 1010) rate. This means that the eye diagrams so acquired would be “information shallow.”
This becomes a problem when issues arise that occur infrequently. For example, these may be pattern related, noise related, or may be related to other effects such as crosstalk and other forms of interference. These conditions may not present themselves on a sampled oscilloscope eye pattern but may operate to prevent a transmission link from achieving desired performance levels. For example, a transmission link may be required to have better than one error in 1012 while the acquired eye diagrams struggle to show events with probabilities below an occurrence rate of 1 in 105.
Eye diagrams provide useful information about characteristics of transmitted data signals and a variety of techniques have been developed to generate and analyze eye diagram data. Integrated circuits (ICs) have I/O speeds that make it desirable to use the techniques without having to interface the signals under test over long distances to a tester. It is obviously desirable to acquire the voltage/time data on-chip and then reconstruct the eye-diagram without the limitations of a display oscilloscope.
Modern computer systems can have hundreds of communication channels per die, making it impractical to view the eye diagram of each individual channel using external test equipment. One solution might be to incorporate components used in a traditional sampling oscilloscope (i.e., trigger, delay line and sampler) near the termination or sample latch of each receiver. However, distribution of a high speed synchronous trigger signal across hundreds of channels is impractical. If the system clock or a locally recovered clock is used, then a variable delay line is required for each sampler. In modern CMOS processes, it is exceptionally difficult to realize a delay line with both fine resolution (i.e., less than an inverter delay—a few picoseconds) and with a large delay range (hundreds of picoseconds). Delay lines often have poor accuracy, high power dissipation and large area, making them impractical for use on a per-channel bases.
In addition, the frequency of the system clock is often dithered slightly to avoid radiation at a particular frequency. In synchronous links, the system clock is common so the frequency deviation is tracked across all communication links. In asynchronous systems, a clock and data recovery block is used on a per channel basis to track the frequency offset of any incoming data signal. Thus the solutions for measuring the eye diagram must have the ability to overcome frequency drift.
Multiple methods have been developed that allow measurements of signal characteristics using asynchronous sampling, on-chip storage of the voltage/time samples and readout of the sampled data for off-chip reconstruction of signal statistics and analysis. These methods all have FIFO memory blocks that allow the capture of relatively large signal data sets (e.g., >4000 samples). These memory blocks become significant when these on-chip measurement techniques are used with wide bus channels.
There is, therefore, a need for a method for making high quality measurements of high speed signals on-chip using circuitry that reduces the area required for the on-chip memory of prior art systems.